1. Field of the Invention
The present invention relates to a semiconductor device to which a semiconductor chip having a cell such as a MOS-type power device is incorporated.
2. Related Art
In recent years, scale-down is demanded from a power device such as a vertical MOSFET, and a reduction in the value of internal resistance (on-state resistance or the like) of the entire semiconductor device including the aforementioned device is also strongly demanded. FIG. 20 shows an example of a related semiconductor device. Here, 2001 denotes a semiconductor substrate, 2002 denotes a source electrode, 2003 denotes a lead frame, 2004 denotes a source wire, 2005 denotes a gate wire, and 2006 denotes a gate wiring.
A lead-out wiring region and a cell forming region are provided on the surface of a semiconductor chip, and a cell such as a MOSFET is formed in the cell forming region. The source electrode 2002 and the lead frame 2003 are connected by a plurality of source wires 2004. The source electrode is required to pass more current than a gate electrode, but since it is connected by the wires, the cross-sectional area of a current path is small, and hence the resistance value is high. To reduce this resistance value, there is a technique in which a reduction in on-state resistance is achieved by a structure in which the source electrode and the lead frame are connected by an almost platy conductive plate. Hereinafter, this almost platy conductive plate is called a strap. Moreover, the structure in which the source electrode and the lead frame are connected by the strap is called a strap structure. For example, in Japanese Patent Laid-open No. 2000-114445, a method of connecting a Cu strap onto an electrode on the surface of a semiconductor chip by an Ag paste as an adhesive is disclosed.
This method has the following problem depending on conditions. Namely, if a temperature cycling test, one of common reliability tests of a semiconductor device, in which the semiconductor device is disposed under an environment with a wide range of temperature and a sharp temperature change, is repeated a plurality of times, there arises a problem that a fault such as cracking occurs in the vicinity of an interface since thermal efficient coefficients of an electrode member, the adhesive, and the strap are different from one another, whereby the life of the semiconductor device is shortened.
As a technique to solve this problem, a method of directly connecting the strap to the electrode on the. surface of the semiconductor chip by ultrasonic bonding is newly proposed. FIG. 21 is a fragmentary sectional view of a related semiconductor device and shows a lead-out wiring region including a gate wiring and the like. It shows a region corresponding to the line A-A′ in FIG. 20, and it is a sectional view of a first lead-out wiring region sandwiched between source electrodes out of the lead-out wiring region. A device such as a MOSFET is formed in another cell forming region, and an N-type source region (not shown) is selectively formed on the surface of a P-type base region 2102 formed on a semiconductor substrate 2101. A first insulating film 2103 is formed on the P-type base region 2102. A first gate wiring 2104 is formed on part of the first insulating film 2103, and the first gate wiring 2104 is connected to a gate electrode (not shown) such as the MOSFET formed in another cell forming region.
A first interlayer dielectric 2106 is formed on a side surface and part of an upper surface of the first gate wiring 2104 for insulation from a source electrode 2105. A second gate wiring 2107 made of Al (Aluminum) is formed on the upper surface of the first gate wiring 2104 on which the first interlayer dielectric 2106 is not formed. The source electrode 2105 is formed on the P-type base region 2102 and the N-type source region. An upper surface of the second gate wiring 2107 is formed higher than an upper surface of the source electrode 2105. A protective film 2108 such as polyimide is formed on part of the source electrode 2105 and on the second gate wiring 2107. The protective film 2108 is formed in order to prevent a short-circuit between the second gate wiring 2107 and a strap formed thereabove, a short-circuit between the second gate wiring 2107 and the source electrode 2105, corrosion of Al, and the like. The source electrode 2105 is connected to a strap 2109 by ultrasonic bonding.
FIG. 22 is a fragmentary sectional view of the related semiconductor device and shows another lead-out wiring region including the gate wiring and the like. It is a sectional view of a region corresponding to the line B-B′ in FIG. 20 and shows an outer peripheral region of the cell forming region out of the lead-out wiring region. It is a sectional view of a second lead-out wiring region in which a gate electrode and the lead frame are connected by the gate wire.
A first insulating film 2202 is formed on a semiconductor substrate 2201. A first gate wiring 2203 is formed on part of the first insulating film 2202, and a first interlayer dielectric 2204 is formed on a side surface and part of an upper surface of the first gate wiring 2203. A second gate wiring 2205 made of Al is formed on the upper surface of the first gate wiring 2203 on which the first interlayer dielectric 2204 is not formed, and an end portion of the second gate wiring 2205 is formed to extend onto the first insulating film 2202. A wiring portion which extends onto the first insulating film 2202 is used as a gate electrode 2207. A source electrode 2206 is formed apart from the gate electrode 2207, and a protective film 2208 such as polyimide is formed on part of the source electrode 2206 and on part of the gate electrode 2207 in order to prevent a short-circuit between the gate electrode 2207 and the source electrode 2206 and corrosion of Al. The source electrode 2206 is connected to the strap by ultrasonic bonding, and the gate electrode 2207 is connected to the gate wire (not shown). A stopper region 2209 is formed in a surface region of an outer peripheral edge of the semiconductor substrate 2201.
FIG. 23 to FIG. 25 show a method of manufacturing a semiconductor device in the first and second lead-out wiring regions shown in FIG. 21 and FIG. 22. The cell forming region is omitted.
As shown in FIG. 23, a P-type base region 2302 is formed on a semiconductor substrate 2301 in the first lead-out wiring region. Subsequently, first insulating films 2303a and 2303b are formed on the P-type base region 2302 and the semiconductor substrate 2301 of the first and second lead-out wiring regions, respectively. Polysilicon is deposited on the first insulating films 2303a and 2303b and etched to form first gate wirings 2304a and 2304b on part of each of the first insulating films 2303a and 2303b in the first and second lead-out wiring regions. Silicon nitride films are formed on upper surfaces and side surfaces of the first gate wirings 2304a and 2304b and etched to form first interlayer dielectrics 2305a and 2305b having slot portions such that part of each of the upper surfaces of the, first gate wirings 1204a and 1204b is exposed.
Then, Al is deposited and etched to form a second gate wiring 2306a in the first lead-out wiring region and a gate electrode 2307 integrated with a second gate wiring 2306b in the second lead-out wiring region. A source electrode 2308 is formed in the cell forming region (only part of the source electrode is shown). The gate electrode 2307 formed in the second lead-out wiring region is formed on the first insulating film 2303b. The source electrode 2308 is formed apart from the second gate wiring 2306a and the gate electrode 2307. A stopper region 2309 is formed in a surface region of an outer peripheral edge of the second lead-out wiring region.
Next, as shown in FIG. 24, polyimide 2310 is deposited in the first and second lead-out wiring regions.
Thereafter, by applying a resist film and forming a resist pattern, a protective film such as covers the gate wiring and a protective film 2311 such that part of the upper surface of the gate electrode is exposed are formed as shown in FIG. 25. Subsequently, the strap (not shown) is formed on the cell forming region and the first lead-out wiring region, and the gate wire (not shown) is formed on the gate electrode 2307 formed in the second lead-out wiring region and connected to the lead frame.
However, reliability to heat increases dramatically in ultrasonic bonding, but since the strap is bonded by applying ultrasonic waves to a predetermined region of the strap, if the ultrasonic waves are-applied to a region on the projecting gate wiring in the first lead-out wiring region, a large shock is applied to the protective film on the gate wiring. Consequently, the projecting gate wiring is crushed, and the gate wiring and the source electrode are deformed, which causes a problem that a short-circuit between the gate wiring and the source electrode occurs, or the protective film formed on the gate wiring deteriorates to cause a short-circuit between the strap and the gate wiring. The aforementioned problem does not arise unless the projecting upper-layer gate wiring with low resistance is formed in the upper portion, but there is a problem that the existence of the upper-layer gate wiring exerts a large influence on internal resistance, and if the upper-layer gate wiring is not formed, for example, a resistance value of approximately 1.5 Ω increases to 3 Ω which is almost twice. In a power MOSFET especially used for synchronous rectification in recent years, an increase in resistance value lowers conversion efficiency, and hence it is not suitable for this use.